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Re: IARCS Verification Seminar Series -- Talk by KC Sivaramakrishnan on Nov. 18 at 1900 hrs IST

by KC Sivaramakrishnan

Thanks Deepak. Kind Regards KC Sivaramakrishnan On Tue, 18 Nov 2025 at 21:01, Deepak D'Souza <deepakd(a)iisc.ac.in> wrote: > Thanks for the clarification KC. And thanks for a great talk. > > Kudos to you and Sheera and the rest of the team for seeing thru a very > challenging and impactful piece of work. > > Best wishes, > > Deepak > > Sent from Android device > > On 18 Nov 2025 20:32, KC Sivaramakrishnan <kcsrk(a)cse.iitm.ac.in> wrote: > External Email > > > > Thanks for coming to my talk today. Apologies for going over. > > Reg one of the questions in the talk about graph isomorphism, Sheera tells > me that `successors` returns a sequence (functional list) of successors in > the order in which they appear in the object. So `successors g_init x == > successors g_sweep x` ensures that pointers are not reordered in an object > between the initial and the final heaps. > > Kind Regards > KC > > On Tue, Nov 18, 2025 at 1:43 AM VSS IARCS <vss.iarcs(a)gmail.com> wrote: > > > Dear all, > > > > The next talk in the IARCS Verification Seminar Series will be given by > KC > > Sivaramakrishnan, an Assistant Professor in the Computer Science and > > Engineering department at Indian Institute of Technology, Madras and the > > Chief Technology Officer of Tarides. The talk is scheduled on Tuesday, > > November 18, at 1900 hrs IST (add to Google calendar > > < > > > https://calendar.google.com/calendar/event?action=TEMPLATE&tmeid=NjNrcmQ1c2… > > > > > ). > > > > The details of the talk can be found on our webpage ( > > https://fmindia.cmi.ac.in/vss/), and also appended to the body of this > > email. > > > > The Verification Seminar Series, an initiative by the Indian Association > > for Research in Computing Science (IARCS), is a monthly, online > > talk-series, broadly in the area of Formal Methods and Programming > > Languages, with applications in Verification and Synthesis. The aim of > this > > talk-series is to provide a platform for Formal Methods researchers to > > interact regularly. In addition, we hope that it will make it easier for > > researchers to explore newer problems/areas and collaborate on them, and > > for younger researchers to start working in these areas. > > > > All are welcome to join. > > > > > > Best regards, > > Organizers, IARCS Verification Seminar Series > > > > ============================================================= > > > > Title: A Mechanically Verified Garbage Collector for OCaml > > > > Meeting Link: > > > https://us02web.zoom.us/j/89164094870?pwd=eUFNRWp0bHYxRVpwVVNoVUdHU0djQT09 > > (Meeting ID: 891 6409 4870, Passcode: 082194) > > > > Abstract: > > OCaml is a garbage-collected (GC) language, where unused memory is > > automatically and reliably freed. OCaml's GC is known for its high > > throughput and low latency, making it suitable for both batch jobs and > > interactive systems. OCaml GC is non-trivial and written in C, and is a > > part of the trusted computing base of OCaml programs. Bugs in the GC have > > the potential to violate the type safety of OCaml programs. In this > talk, I > > will describe our work in developing a correct, proof-oriented GC for > OCaml > > from scratch, capable of being swapped into the existing OCaml runtime > > system. Our GC is simple — a stop-the-world mark-and-sweep collector — > but > > is capable of running non-trivial OCaml programs. The GC is developed in > F* > > and its low-level subset Low*, which is compiled to memory-safe C. I will > > also describe the extension of our collector to enable generational and > > incremental collection. > > > > This work was published in the Journal of Automated Reasoning (link > > <https://link.springer.com/article/10.1007/s10817-025-09721-0>). > > > > Bio: KC Sivaramakrishnan is an Assistant Professor in the Computer > Science > > and Engineering department at Indian Institute of Technology, Madras and > > the Chief Technology Officer of Tarides. He led the development of > > Multicore OCaml, a concurrent and parallel extension of the OCaml > > programming language. His research interest lies in building robust, > secure > > and scalable systems using programming language technology. > > _______________________________________________ > > FMIndia mailing list -- fmindia(a)cmi.ac.in > > To unsubscribe send an email to fmindia-leave(a)cmi.ac.in > > > > https://fmindia.cmi.ac.in/ > > _______________________________________________ > > > > > -- > Kind Regards > KC Sivaramakrishnan > _______________________________________________ > FMIndia mailing list -- fmindia(a)cmi.ac.in > To unsubscribe send an email to fmindia-leave(a)cmi.ac.in > > https://fmindia.cmi.ac.in/ > _______________________________________________ >

7 hours, 3 minutes

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IARCS Verification Seminar Series -- Talk by KC Sivaramakrishnan on Nov. 18 at 1900 hrs IST

by VSS IARCS

Dear all, The next talk in the IARCS Verification Seminar Series will be given by KC Sivaramakrishnan, an Assistant Professor in the Computer Science and Engineering department at Indian Institute of Technology, Madras and the Chief Technology Officer of Tarides. The talk is scheduled on Tuesday, November 18, at 1900 hrs IST (add to Google calendar <https://calendar.google.com/calendar/event?action=TEMPLATE&tmeid=NjNrcmQ1c2…> ). The details of the talk can be found on our webpage ( https://fmindia.cmi.ac.in/vss/), and also appended to the body of this email. The Verification Seminar Series, an initiative by the Indian Association for Research in Computing Science (IARCS), is a monthly, online talk-series, broadly in the area of Formal Methods and Programming Languages, with applications in Verification and Synthesis. The aim of this talk-series is to provide a platform for Formal Methods researchers to interact regularly. In addition, we hope that it will make it easier for researchers to explore newer problems/areas and collaborate on them, and for younger researchers to start working in these areas. All are welcome to join. Best regards, Organizers, IARCS Verification Seminar Series ============================================================= Title: A Mechanically Verified Garbage Collector for OCaml Meeting Link: https://us02web.zoom.us/j/89164094870?pwd=eUFNRWp0bHYxRVpwVVNoVUdHU0djQT09 (Meeting ID: 891 6409 4870, Passcode: 082194) Abstract: OCaml is a garbage-collected (GC) language, where unused memory is automatically and reliably freed. OCaml's GC is known for its high throughput and low latency, making it suitable for both batch jobs and interactive systems. OCaml GC is non-trivial and written in C, and is a part of the trusted computing base of OCaml programs. Bugs in the GC have the potential to violate the type safety of OCaml programs. In this talk, I will describe our work in developing a correct, proof-oriented GC for OCaml from scratch, capable of being swapped into the existing OCaml runtime system. Our GC is simple — a stop-the-world mark-and-sweep collector — but is capable of running non-trivial OCaml programs. The GC is developed in F* and its low-level subset Low*, which is compiled to memory-safe C. I will also describe the extension of our collector to enable generational and incremental collection. This work was published in the Journal of Automated Reasoning (link <https://link.springer.com/article/10.1007/s10817-025-09721-0>). Bio: KC Sivaramakrishnan is an Assistant Professor in the Computer Science and Engineering department at Indian Institute of Technology, Madras and the Chief Technology Officer of Tarides. He led the development of Multicore OCaml, a concurrent and parallel extension of the OCaml programming language. His research interest lies in building robust, secure and scalable systems using programming language technology.

8 hours, 42 minutes

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RHPL@FSTTCS 2025: Call for Participation

by abhisekh.sankaran＠tcs.com

======================= Call for Participation ======================= ============================================================= RHPL@FSTTCS 2025: Workshop on Research Highlights in Programming Languages + Website: https://fmindia.cmi.ac.in/rhpl2025/ + Dates: December 17 - 19, 2025 + Venue: BITS Pilani, K K Birla Goa Campus, co-located with FSTTCS 2025 + Early registration deadline: November 30, 2025 + Registration page: https://fmindia.cmi.ac.in/rhpl2025/registration ============================================================= =================== About the Workshop =================== RHPL 2025 is the fourth edition of the Workshop on Research Highlights in Programming Languages (RHPL) organized by the Indian Association for Research in Computing Science (IARCS). The focus of the workshop is on all areas of Programming Languages (PL), including but not limited to: + Applied formal methods + Automated and interactive theorem provers + Compilers + Concurrency and memory models + Domain and type theories + Program analysis and verification + Program sketching, synthesis and repair + Programming language design and semantics Further, in view of the increasing role of Artificial Intelligence (AI) and Machine Learning (ML) in PL theory and practice, the workshop also includes in its scope themes pertaining to the influences of AI/ML concepts and tools on the mentioned PL topics, and vice-versa; for instance, probabilistic programming languages. The objective of RHPL is to foster interactions between the attendees of the workshop, and more broadly, between researchers working on Programming Languages and the traditional FSTTCS community of researchers working on Theoretical Computer Science and Formal Methods. RHPL 2025 will be held at BITS Pilani, K K Birla Goa Campus as a co-located workshop of FSTTCS 2025. RHPL 2025 website: https://fmindia.cmi.ac.in/rhpl2025/ ================= Panel Discussion ================= + Theme: Bridging PL Theory and Practice in the Age of AI + Panelists: - Uday Khedker (IIT Bombay) - Pavithra Prabhakar (Kansas State University) - Subhajit Roy (IIT Kanpur) - R Venkatesh (TCS Research) =========================== Accepted Talks and Posters =========================== The list of accepted talks and posters of RHPL 2025 can be found at the link below. https://fmindia.cmi.ac.in/rhpl2025/accepted_proposals ============== Registration ============== The registration for RHPL 2025 is open. - Early registration deadline: *November 30, 2025* - Registration page: https://fmindia.cmi.ac.in/rhpl2025/registration ================== Local Information ================== - Local information page: https://fmindia.cmi.ac.in/rhpl2025/local_information ===================== Organising Committee ===================== - Abhisekh Sankaran (TCS Research) (co-Chair) - Divyesh Unadkat (Synopsys) (co-Chair) - Deepak D'Souza (IISc Bangalore) - Uday Khedker (IIT Bombay) - Kumar Madhukar (IIT Delhi) - Kartik Nagar (IIT Madras) - Sumanth Prabhu (TCS Research) - Ganesan Ramalingam (Microsoft) - Abhik Roychoudhury (National University of Singapore) ========= Contact ========= Feel free to write to us with any queries at the following email addresses. - abhisekh.sankaran(a)tcs.com - divyesh.unadkat(a)synopsys.com We look forward to seeing you in Goa. Best regards, RHPL 2025 Organising Committee RHPL 2025 Website: https://fmindia.cmi.ac.in/rhpl2025/

1 day, 18 hours

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10th Indian SAT+SMT School (co-located with FSTTCS 2025) -- Call for participation

by VSS IARCS

Dear all, The 10th edition of the Indian SAT+SMT School will be held during 14-15 December 2025, at BITS Pilani, K K Birla Goa Campus, co-located with FSTTCS 2025. Please visit the webpage (https://sat-smt.in/) for details on invited speakers, registration, etc. The early bird registration for the school closes on November 30th. SAT+SMT School 2025 will also host a session for posters and short talks -- a forum for students, faculty and industry practitioners working in the broad area of SAT/SMT solving to present their research work to the school attendees. Early-stage ideas are more than welcome. We anticipate it to be an excellent opportunity to get feedback, and network with peers and experts in the field. If you are interested in presenting a poster or giving a short talk, please submit an entry (just a title and a short abstract) using this Google form <https://forms.gle/5K7DyDpZtPpMRuM3A>. The submission deadline is Nov. 29th. Accepted entries will be notified by Dec. 2nd. The final selection will be made by the organizing committee based on the availability of slots and relevance to the school. In case you have submitted an entry already, and your decision to register for the school depends on its acceptance, please let us know immediately by writing to Priyanka (pgolia(a)cse.iitd.ac.in) and Madhukar (madhukar(a)cse.iitd.ac.in). We look forward to your participation. Needless to say, we'd be very happy to clarify any questions you might have in this regard. Feel free to write to us at indian.satsmt.school(a)gmail.com <mailto:indian.satsmt.school@gmail.com <indian.satsmt.school(a)gmail.com>>. Best regards, Supratik Chakraborty, IIT Bombay Priyanka Golia, IIT Delhi Ashutosh Gupta, IIT Bombay Saurabh Joshi, SupraOracles Kumar Madhukar, IIT Delhi Kuldeep S. Meel, Georgia Institute of Technology Aalok Thakkar, Ashoka University

3 days, 5 hours

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IARCS Verification Seminar Series -- Talk by KC Sivaramakrishnan on Nov. 18 at 1900 hrs IST

by VSS IARCS

Dear all, The next talk in the IARCS Verification Seminar Series will be given by KC Sivaramakrishnan, an Assistant Professor in the Computer Science and Engineering department at Indian Institute of Technology, Madras and the Chief Technology Officer of Tarides. The talk is scheduled on Tuesday, November 18, at 1900 hrs IST (add to Google calendar <https://calendar.google.com/calendar/event?action=TEMPLATE&tmeid=NjNrcmQ1c2…> ). The details of the talk can be found on our webpage ( https://fmindia.cmi.ac.in/vss/), and also appended to the body of this email. The Verification Seminar Series, an initiative by the Indian Association for Research in Computing Science (IARCS), is a monthly, online talk-series, broadly in the area of Formal Methods and Programming Languages, with applications in Verification and Synthesis. The aim of this talk-series is to provide a platform for Formal Methods researchers to interact regularly. In addition, we hope that it will make it easier for researchers to explore newer problems/areas and collaborate on them, and for younger researchers to start working in these areas. All are welcome to join. Best regards, Organizers, IARCS Verification Seminar Series ============================================================= Title: A Mechanically Verified Garbage Collector for OCaml Meeting Link: https://us02web.zoom.us/j/89164094870?pwd=eUFNRWp0bHYxRVpwVVNoVUdHU0djQT09 (Meeting ID: 891 6409 4870, Passcode: 082194) Abstract: OCaml is a garbage-collected (GC) language, where unused memory is automatically and reliably freed. OCaml's GC is known for its high throughput and low latency, making it suitable for both batch jobs and interactive systems. OCaml GC is non-trivial and written in C, and is a part of the trusted computing base of OCaml programs. Bugs in the GC have the potential to violate the type safety of OCaml programs. In this talk, I will describe our work in developing a correct, proof-oriented GC for OCaml from scratch, capable of being swapped into the existing OCaml runtime system. Our GC is simple — a stop-the-world mark-and-sweep collector — but is capable of running non-trivial OCaml programs. The GC is developed in F* and its low-level subset Low*, which is compiled to memory-safe C. I will also describe the extension of our collector to enable generational and incremental collection. This work was published in the Journal of Automated Reasoning (link <https://link.springer.com/article/10.1007/s10817-025-09721-0>). Bio: KC Sivaramakrishnan is an Assistant Professor in the Computer Science and Engineering department at Indian Institute of Technology, Madras and the Chief Technology Officer of Tarides. He led the development of Multicore OCaml, a concurrent and parallel extension of the OCaml programming language. His research interest lies in building robust, secure and scalable systems using programming language technology.

3 days, 17 hours

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CfP: REVERSIBLE COMPUTATION 2026 –18th International Conference on Reversible Computation, July 9–10, 2026, Torino, Italy

by Clément Aubert

Call for papers REVERSIBLE COMPUTATION 2026 18th International Conference on Reversible Computation July 9th - July 10th, 2026, Torino, Italy <https://reversible-computation.github.io/> Purpose & Scope =============== Reversible computation has a growing number of promising application areas such as low-power electronics, encoding/decoding, debugging, testing and verification, database recovery, discrete event simulation, the modeling of biochemical systems, and reversible algorithms, specification formalisms, programming languages and process algebras. Furthermore, reversible logic provides a basis for quantum computation with its applications, for example, in cryptography and in the development of highly efficient algorithms. First reversible circuits and quantum circuits have been implemented and are seen as promising alternatives to conventional CMOS technology. The 18th edition of the Reversible Computation conference will bring together researchers from computer science, mathematics, and physics to discuss new developments and directions for future research in Reversible Computation, including applications of reversibility to quantum computation. Research papers, tutorials, tool demonstrations, and work-in-progress reports are within the scope of the conference. Contributions on all areas of Reversible Computation are welcome, including---but not limited to---the following topics: - Applications - Architectures - Algorithms - Bidirectional transformations - Circuit Design - Debugging - Fault Tolerance and Error Correction - Hardware - Information Theory - Physical Realizations - Programming Languages - Program Transformation and Optimisation - Quantum Computation - Software - Synthesis - Theoretical Results - Testing - Verification Important dates =============== Abstract submission: February 6th, 2026 AOE Submission deadline: February 13th, 2026 AOE Notification to authors: April 22nd, 2026 AOE Final version: May 13th, 2026 AOE Conference: July 9th - July 10th, 2026 Submission guidelines ===================== The Reversible Computation conference welcomes the following types of submissions: - full research papers (15 pages maximum, not including references), - tutorials (15 pages maximum, not including references), - work-in-progress (6 pages maximum, not including references), - tool demonstration papers (6 pages maximum, not including references), to be submitted at <https://easychair.org/conferences?conf=rc2026>. Please do not forget to clearly indicate the type of your submission by choosing the proper category on the submission page. Additional material intended for reviewers but not for publication in the final version---for example, details of proofs---may be placed in a clearly marked appendix that is not included in the page limit. Reviewers are at liberty to ignore appendices and papers must be understandable without them. The paper submission will be accepted as a PDF file using Springer's LNCS style (<https://www.springer.com/gp/computer-science/lncs/conference-proceedings-gu…>). Authors are encouraged to include their ORCID (<https://orcid.org/>) number in the paper. At least one author of each accepted paper is expected to register and present the paper at the conference. We would appreciate if one person would not present more than two papers at the conference: if more than two papers are accepted by a group of authors, we kindly ask that the papers be presented by different co-authors, as far as possible. All accepted papers will be included in the conference proceedings and published by Springer as a LNCS volume. Proceedings authors will be expected to adhere to Springer's Book Authors' Code of Conduct (<https://www.springernature.com/gp/authors/book-authors-code-of-conduct>). Invited Talks ============== Reversible Computation 2026 will feature invited talks by Hannah Earley (<https://ha.nnah.io/>) and Prakash Panangaden (<https://www.cs.mcgill.ca/~prakash/>). Details will be posted at <https://reversible-computation.github.io/invited/>. Programme Committee =================== - Clément Aubert (co-chair) (Augusta University) - Bogdan Aman (Academia Română Filiala Iași) - Jacques Carette (McMaster University) - Kostia Chardonnet (INRIA) - Kamalika Datta (Universität Bremen) - Alessandra Di Pierro (Università di Verona) - Stefano Gogioso (University of Oxford) - Anna Gogolińska (Nicolaus Copernicus University in Torun) - Robin Kaarsgaard (Syddansk Universitet) - Jarkko Kari (Turun yliopisto) - Ivan Lanese (Università di Bologna & INRIA) - Doriana Medić (Università degli studi di Torino) - Uwe Meyer (Universität Gießen) - Torben Mogensen (Københavns Universitet) - Mathys Rennela (Welinq) - Neil J. Ross (Dalhousie University) - Luca Roversi (co-chair) (Università degli studi di Torino) - Amr Sabry (Indiana University) - Yasuhiro Takahashi (University of Tsukuba) - Shoji Yuen (Nagoya daigaku) Organizing Committee ==================== - Luca Paolini (chair) (Università degli studi di Torino) - Doriana Medić (Università degli studi di Torino) - Mario Bifulco (Università degli studi di Torino) - Matteo Palazzo (Università degli studi di Torino) - Luca Roversi (Università degli studi di Torino) Steering Committee ================== - Robert Glück (Københavns Universitet) - Ivan Lanese (Università di Bologna & INRIA) - Łukasz Mikulski (Uniwersytet Mikołaja Kopernika w Toruniu) - Irek Ulidowski (University of Leicester & AGH University of Science and Technology) - Germán Vidal (Universitat Politècnica de València) Patronages & Sponsor ==================== Reversible Computation 2026 is under the patronage of the Università degli studi di Torino (<https://www.unito.it/>) and its Dipartimento di Informatica (<https://informatica.unito.it/do/home.pl>), and is sponsored by Vaire (<https://vaire.co/>). -- Clément Aubert, Associate Professor of Computer Science, School of Computer and Cyber Sciences, Augusta University, https://spots.augusta.edu/caubert/

6 days, 21 hours

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IWSLA 2025: Call for Participation

by abhisekh.sankaran＠tcs.com

======================= Call for Participation ======================= ============================================================= Indian Winter School on Logic and its Applications (IWSLA) 2025 + Website: https://iwsla25.csisbitsgoa.com + Dates: December 8 - 12, 2025 + Venue: BITS Pilani, K K Birla Goa Campus ============================================================= ================= About the School ================= The Indian Winter School on Logic and its Applications (IWSLA) 2025 is organized under the auspices of the Association for Logic in India (ALI) (https://logicindia.org). The aim of the school is to bring together students, researchers, and practitioners from computer science, mathematics, philosophy, and linguistics who share an interest in the study and application of logic. The school is especially aimed at graduate students, early-career researchers, and anyone interested in exploring the role of logic across disciplines. ======================== Courses and Instructors ======================== + Course on Lean (Theorem Proving) - Instructor: Dr. T. V. H. Prathamesh, KREA University - Invited Lecture: Prof. Siddhartha Gadgil, IISc Bangalore + Course on Forcing (Set Theory) - Instructor: Dr. Ashutosh Kumar, IIT Kanpur ================ Important Dates ================ + Early Registration Deadline: November 21, 2025 (earlier: November 15, 2025) + School Dates: December 8 - 12, 2025 Please note that the number of participants is limited. Selection will be on **first-come, first-served** basis. ============== Registration ============== Registration for IWSLA 25 is now open. Participants may register through the form linked below. Registration Form: https://forms.gle/ke4XoW7X4cUvKVAAA ---------------- Registration Fees: ---------------- + Students: ₹ 2500 /- + Faculty: ₹ 5000 /- + Industry: ₹ 10000 /- ------ Note: ------ 1. The registration fee is non-refundable. 2. We host a limited number of participants and registration will be on a first-come, first-served basis. 3. Shared accommodation is arranged for girls on campus and for boys outside the campus (shuttle will be arranged) on a payment basis separately. 4. Participants from academia and industry may book accommodation in the nearby hotels. 5. Make the payment first and then fill the form. ============== Payment Link ============== Participants may follow the steps below to make the payment. 1. Search for "BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE" at the following link. Pay via SBI Collect: https://onlinesbi.sbi.bank.in/sbicollect/icollecthome.htm 2. Select "BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE Goa" from the dropdown menu. 3. Choose the payment category as "IWSLA25". 4. Complete the payment details and make the payment. ===================== Organising Committee ===================== Diptendu Chatterjee, BITS Pilani, K K Birla Goa Campus ==================== Programme Committee ==================== A Baskar, BITS Pilani, K K Birla Goa Campus Sourav Tarafder, St. Xavier's College, Kolkata ========== Hosted by ========== Department of Computer Science & Information Systems, BITS Pilani, K K Birla Goa Campus In association with Association for Logic in India (ALI) ======= Venue ======= Birla Institute of Technology & Science, Pilani K K Birla Goa Campus NH - 17B, Zuarinagar, Goa - 403726, India Tel: +91-832-2580221, +91-832-2580811 ========= Contact ========= + Email: diptenduc(a)goa.bits-pilani.ac.in + Phone: +91-832-2580221 / +91-832-2580811 ============== How to Reach ============== + Goa International Airport (Dabolim): 7 km + Mopa Airport (Manohar International): 56 km + Vasco-da-Gama: 10 km south + Margao: 20 km north We look forward to your participation and to an engaging week of lectures and discussions on logic and its applications. Warm regards, Organising Committee Indian Winter School on Logic and its Applications (IWSLA) '25 BITS Pilani, K K Birla Goa Campus Website: https://iwsla25.csisbitsgoa.com

1 week, 4 days

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Blockchain Kaigi 2025 (BCK25), IIT Bombay

by Madhavan Mukund

----- Forwarded message from Vishwas Patil <ivishwas(a)gmail.com> ----- From: Vishwas Patil <ivishwas(a)gmail.com> To: Madhavan Mukund <madhavan(a)cmi.ac.in> Date: Fri, 31 Oct 2025 02:59:55 +0530 Dear All, The draft program of Blockchain Kaigi 2025 (BCK25) - *The 5th International Workshop on Blockchain* is available. *We invite you to register and participate in this workshop.* *Dates*: December 4-6, 2025 *Venue*: PC Saxena Auditorium, IIT Bombay *Registration*: https://bck-2025.isrdc.in/registration/ (Students doing research in Blockchain can register for free by uploading a recommendation letter from their advisor) *Keynotes & Invited Talks* by: (Abstracts: https://bck-2025.isrdc.in/speakers/) 1. Dilip Asbe, Managing Director and CEO of the National Payments Corporation of India 2. Jun Watanabe, Chairman, Sony Block Solutions Labs Pte. Ltd 3. Kazumasa Omote, Professor, University of Tsukuba 4. Hidenori Nakazato, Professor, Waseda University 5. Suvendu Pati, Chief General Manager of Reserve Bank of India (RBI) 6. Ikkei Matsuda, CEO of Digital Platformer The program will have 38 full-paper presentations & 13 poster presentations on various topics in Blockchain. (List of *accepted papers*: https://bck-2025.isrdc.in/accepted-papers/) There will be a few *Panel Discussions* involving industry professionals, policy-makers, and leading international researchers. Blockchain Kaigi 2025: https://bck-2025.isrdc.in Register here: https://bck-2025.isrdc.in/registration/ -- Yours sincerely, Vishwas Patil. Senior Scientist, IIT Bombay. https://sites.google.com/site/ivishwas <http://sites.google.com/site/ivishwas> An omission is the most powerful form of lying. ~ George Orwell. ----- End forwarded message -----

2 weeks, 4 days

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Call for Submissions and Participations -- WAGS@FSTTCS 2025

by Suman Sadhukhan

**Apologies for multiple postings** Dear Colleagues, Please find below the call for participation and talks for the Workshop on automata and games for synthesis, taking place just after FSTTCS at BITS Goa. Kindly share it with others. ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -------------------------------------- Call for Participations Workshop on Automata and Games for Synthesis <https://sites.google.com/view/wagsfsttcs2025/home> Goa, India December 20th, 2025 Co-located with Foundations of Software Technology and Theoretical Computer Science (FSTTCS) 2025 <https://www.fsttcs.org.in/2025/> --------------------------------------------------------------------------------------------- Submission of contributed talks at: https://forms.gle/baHEbDRh5eJbfgbA8 --------------------------------------------------------------------------------------------- Workshop website: https://sites.google.com/view/wagsfsttcs2025 =================== About the workshop =================== The second iteration of the *Workshop on Automata and Games for Synthesis* is an on-site event happening on December 20, 2025, in Goa, India. It is co-located with Foundations of Software Technology and Theoretical Computer Science (FSTTCS) 2025, the premier international computer science conference in India, and held annually in December since 1981. Automated synthesis of systems from specifications has been a longstanding goal of computer science. The workshop focuses on various aspects by which automata and game solving are used to tackle problems motivated by synthesis. The workshop will feature three invited speakers and some sessions with short presentations. For the short presentations, early-career researchers are encouraged to talk about their research in 10–15 minute sessions (exact length will depend on the number of contributions). For submission, we solicit a title and an abstract for the talk (please find the Google Form link below). The workshop does not have proceedings; therefore previously published talks or ongoing work are both encouraged to be presented. Topics for presentation at the workshop include, but are not limited to, the following: Automata Theory Reactive Synthesis Games on Finite and Infinite Graphs Computational aspects of Game Theory Concurrency and Distributed computation Formal Languages Games and Automata for Verification Specification and Verification of Finite and Infinite-state Systems ============================ Important dates and information ============================ Early Submission Deadline November 13, 2025 Early Notification November 14, 2025 (notifications sent on a rolling basis; note that early-bird registration for the conference and workshop ends on November 15, 2025) Final Submission Deadline November 25, 2025 (AoE) Final Notification November 30, 2025 Workshop December 20, 2025 Submission of contributed talks at: https://forms.gle/baHEbDRh5eJbfgbA8 ============= Invited speakers ============= Orna Kupferman (Hebrew University) B. Srivathsan (Chennai Mathematical Institute) Aditya Prakash (LIS, Aix-Marseille Université) ============= Organisers ============= Sougata Bose Suman Sadhukhan K.S. Thejaswini ============= Program ============= The detailed program will be available here <https://sites.google.com/view/wagsfsttcs2025/schedule> closer to the workshop. For any queries, contact the organisers: sougata.bose(a)umons.ac.be, suman.sadhukhan00(a)gmail.com, thejaswini.k.s(a)ista.ac.at Best regards, Suman Sadhukhan Postdoctoral Researcher, University of Haifa

3 weeks, 6 days

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APLAS-ATVA 2025 Call for Participation

by Madhavan Mukund

----- Forwarded message from Deepak D'Souza <deepakd(a)iisc.ac.in> ----- From: Deepak D'Souza <deepakd(a)iisc.ac.in> Date: Wed, 24 Sep 2025 06:48:04 +0000 Subject: APLAS-ATVA 2025 Call for Participation APLAS-ATVA 2025 Call for Participation The 23rd editions of the Asian Symposium on Programming Languages and Systems (APLAS 2025) and the International Symposium on Automated Technology for Verification and Analysis (ATVA 2025) will be jointly held at the International Institute for Information Technology, Bangalore (IIIT Bangalore), during 27-31 October 2025. Registrations are now open. Early Registrations close on 30th September 2025. Key highlights of the conferences include: * Invited talks by Aarti Gupta (Princeton U), Peter Mueller (ETH Zurich), and Rahul Sharma (Microsoft Research India) * APLAS and ATVA contributed Research and Tool talks * Tutorials on Replicated Data Types by Kartik Nagar (IIT Madras) and Quantitative and Probabilistic Verification by Benjamin Kaminski (Saarland U) * New Ideas and Emerging Results in Programming Languages and Systems (NIER) Track talks. * Workshop on Milestones and Motifs in Automata and Concurrency, with invited talks by Ahmed Bouajjani (Paris Diderot U), Pavithra Prabhakar (Kanas State U), P S Thiagarajan (UNC Chapel Hill), and Pascal Weil (U Sorbonne Paris Nord). A limited number of travel grants are available, particularly for students. Travel grant applications close on 05 October 2025. For more details visit the conference webpages at https://conf.researchr.org/home/atva-2025 and https://conf.researchr.org/home/aplas-2025. Deepak D'Souza and Pritam Gharat (General Chairs APLAS-ATVA 2025) On behalf of APLAS-ATVA 2025 Organizing Committee ----- End forwarded message -----

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